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AI chips must get the math right

Conference: DVCLUB Europe | Verification of AI Designs
Speaker: Sergio Marchese, Technical Marketing Manager, OneSpin Solutions

Most AI chips and hardware accelerators that power machine learning (ML) and deep learning (DL) applications include floating-point units (FPUs). Algorithms used in neural networks are often based on operations that use multiplication and addition of floating-point values. FPUs are difficult to implement. The IEEE 754 standard defines many corner-case scenarios and non-ordinary values. Even a minor rounding mistake could accumulate over many iterations and produce a large error. An FPU formal verification app compliant with IEEE-754 provides an efficient and rigorous solutions to FPU functional verification.

3 Key Points:

  • Floating-point unit (FPU) for AI chips
  • FPU Formal Verification App
  • Compliance with IEEE-754
Speaker Biography: Sergio Marchese is technical marketing manager at OneSpin Solutions. He has 20 years of experience in electronic chip design, and deployment of advanced hardware development solutions across Europe, North America, and Asia. His expertise covers IC design, functional verification, safety standards, including ISO 26262 and DO-254, and detection of hardware Trojans and security vulnerabilities. He is passionate about enabling the next generation of high- integrity chips that underpin the Internet of Things, 5G, artificial intelligence, and autonomous vehicles.


DVCLUB Europe is made possible through the generosity of our sponsors.

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