About the Speaker

Ahmed Samhan is a Digital Verification Engineer at Alpinum Consulting, where he specialises in RISC-V processor verification and training. He graduated from Ain Shams University, Faculty of Engineering, with a degree in Electronics and Communications Engineering. At Alpinum, Ahmed works on verification projects involving RISC-V CPU cores and SoC-level validation, and contributes to developing training materials for Alpinum’s RISC-V verification course. He is passionate about advancing open-source processor verification and sharing practical verification knowledge with the engineering community.

RISC-V Verification: From CPU Fundamentals to SoC-Level Validation

Overview

This training session provides a comprehensive overview of RISC-V processor verification, combining foundational CPU concepts with practical verification techniques. Attendees will explore the RISC-V ISA architecture, instruction encoding, register files, and control and status registers. The session covers processor microarchitectures from single-cycle to pipelined designs, along with stimulus generation strategies for CPU verification. Moving to SoC-level verification, participants will learn about hierarchical verification approaches, the differences between IP and SoC-level testing, and practical examples using the CVA6 open-source RISC-V core with UVM-based testbenches. The training includes both lecture content and hands-on lab exercises.

Key Points

• Comprehensive coverage of RISC-V ISA fundamentals including instruction encoding, register files, CSRs, interrupts, and exception handling
• Practical CPU verification methodology covering stimulus generation strategies, coverage-driven verification, and processor microarchitecture validation.
• SoC-level verification techniques using the open-source CVA6 RISC-V core, including hierarchical verification, AXI/APB interface testing, and multi-core cache verification.