About the Speaker

Yassine Eben-Aimine is a Product Architect for Formal Tools at Siemens EDA. Yassine has over 25 years experience in the EDA software development and support process. Yassine has been guiding customers through hands-on product evaluations and deployments of digital verification technologies comprising simulation and formal. Yassine holds bachelors and masters degrees in Electronics and Computing from the Institut National Polytechnique in Toulouse, France

Accelerating FPGA development with AI-Powered Design & Verification Workflows

Overview

The dawn of Artificial Intelligence presents a pivotal moment in FPGA design creation and verification. In this talk, I will introduce the Questa One Verification Environment’s as an AI-capable FPGA development tool that:
– provides intelligent RTL development
– leverages powerful LLMs to enable smart editing features, automated templates, and integrated analysis tool
– accelerate your VHDL/Verilog development workflow while maintaining design intent and quality.

Key Points

• LLMs enable a more interactive development experience
  Engineers can use natural-language prompts to rapidly explore, edit, explain, and document HDL-related content
• AI can help engineers move faster without skipping discipline
  Smart editing, templates, and analysis can streamline tasks while supporting structured engineering practices.
• Earlier insight through connected analysis
  Built-in analysis capabilities help engineers detect issues sooner and improve confidence in RTL quality and verification completeness.