About the Speaker

Doug Carson is a device security solution expert working in Edinburgh on hardware security test solutions for the Keysight Device Security Lab. During his career he has architected telecom measurement, processing and security solutions and contributed to innovation projects for critical infrastructure security. Doug has been involved in device security since 2016 as a co-author of a paper on power side channel analysis that is now the reference in the EMB3D™ framework. He currently works on market development activities for device security in Europe

Opensource Verification Tools For Hyperscale Data Centre Silicon

Overview

The Open Compute Project provides a community for hyperscale innovation and has pioneered opensource data centre chips through the Linux Foundation CHIPS Alliance Project. As an accredited lab for OCP S.A.F.E Keysight must assess the security of these devices and integrate with the opensource tools used in their design and verification. In this talk we will share our experience of the verification tooling used with the VeeR-EL2 RISC-V core. A verification workflow using our OpenTAP opensource test automation platform with this tooling will be presented as a case study.

Key Points

• Hyperscalers are driving opensource silicon innovation
• Opensource can benefit hardware security through transparency
• Verification workflow can be automated using opensource tools

Test and Measurement Advances for Semiconductor Supply Chain Assurance

Overview

Semiconductor supply chains are global, complex and vulnerable to interference from adversaries. They are also impossible to re-shore to semiconductor sovereignty can only be achieved through detailed surveillance of the supply chain. In this talk we discuss results of recent academic papers that have applied test equipment to detect hardware trojans or counterfeiting. We will then discuss the signal processing required to detect anomalies in devices. To conclude an overview of the architecture of a security testbench is given to illustrate how test time can be reduced though hardware acceleration.

Key Points

• Academic is advancing post-silicon hardware trojan detection
• High performance signal processing enables detection
• Hardware acceleration scales detection