Practical Asynchronous SystemVerilog Assertions

Nearly all digital designs have asynchronous behaviors or may be inherently asynchronous by design. Likewise, asynchronous behaviors appear in the form of asynchronous handshaking protocols for peripheral devices or in the case of synchronizers between clock domain crossings. SystemVerilog assertions (SVA) provide a great way of testing and describing design behaviors. However, using SVA to capture asynchronous behavior is not always straightforward due to the scheduling semantics of SystemVerilog. While triggering on an asynchronous event is easy enough, the sampling of the assertion inputs is either dependent on its context or synchronous by nature. Often, asynchronous events occur before the design has updated its state, requiring the checking of the RTL to be delayed. Furthermore, the timing of asynchronous events may be hard to predict, making it harder to describe using an assertion. This session will cover eight common asynchronous scenarios and the SVA solutions for checking them.

Doug Smith is a verification engineer and instructor for Doulos based in the Austin Texas area with expertise in SystemVerilog, UVM, and formal verification. At Doulos, he delivers training in verification methodologies, hardware description languages, and formal technology. Doug holds a masters degree in Computer Engineering from the University of Cincinnati and a bachelors degree in Physics and Biology from Northern Kentucky University. Currently, he resides in Paige Texas with his wife and family on a small farm where he raises bees, horses, chickens, and pigs and loves playing around on his tractor.