| Conference: | Verification Futures 2023 (click here to see full programme) |
| Speaker: | Dr David Long |
| Presentation Title: | Is it easy to get started with UVM, or should I use Formal instead? |
| Abstract: | The Universal Verification Methodology (UVM) is an IEEE standard which provides a library of base classes, a framework and rules that enable complex simulation environments to be created in SystemVerilog. Unfortunately, beginners often struggle to understand the multitude of features provided by UVM. This presentation will introduce a subset of UVM, that makes it easier to get started and will show how these can be used to create a simple UVM testbench. However, a simulation-based approach is not always the best way to verify a design: Formal verification is also possible in SystemVerilog! The presentation will conclude with an overview of formal verification in SystemVerilog and consider how to decide the most appropriate approach to take. |
| Speaker Bio: | Dr David Long has been a key member of the Doulos technical team since 2001, specialising in Hardware Description Language-based design and verification. As well as developing, writing, and presenting training courses in leading-edge methodologies for embedded SW development, FPGA, ASIC and SoC design and verification, David regularly contributes to technical papers, tutorials, and conference presentations at major industry events world-wide. He has also provided project support and consultancy for industrial clients in the fields of digital/mixed-signal IC design and verification. Courses taught include: SystemVerilog, SystemC, UVM, VHDL, Verilog, VHDL-AMS, C and C++ Programming for Embedded Systems and Embedded System Security. David was co-author of the IEEE Standard 1666-2005 SystemC Language Reference Manual and wrote the draft LRM for the SystemC Control, Configuration and Inspection (CCI) working group. He has a PhD in Simulation of Mixed-Signal Circuits and a MSc in VLSI Design. Before joining Doulos, David worked for 10 years at a UK university where he was a Senior Lecturer in Microelectronics. In total, he has over 35 years’ experience of electronics design and verification in both industry and academia. |
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