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OneSpin Solutions

Conference: Verification Futures 2018 (click here to see full programme)
Speaker: Sergio Marchese, Technical Marketing Manager. OneSpin Solutions
Presentation Title: Challenges Call for Innovation: A Recipe for Success and a Taste of Formal Solutions
Abstract: Functional verification has been a thorn in the hardware development flow for two decades. Constrained-random simulation, formal verification, and hardware-in-the-loop testbenches have been and still are crucial to keep the monster at bay. In recent years, we have seen safety adding a new, thick layer of complexity to this problem. Security is following suit and, similarly to safety, will likely force its way into the engineering and management culture of many organizations.

Challenges call for innovation, and innovation requires thinking out of the box and allowing for deep changes. EDA companies need to be agile, flexible and tightly engaged with their customers to solve the right problems, and deliver reliable, high-quality solutions quickly. In this presentation, OneSpin offers some insight on its internal processes and culture enabling the development of innovative formal solutions, and presents concrete examples of how formal helps engineering teams worldwide to address their latest challenges.

  • Challenges: Functional Verification, Safety, Security
  • Formal to the rescue: the EDA recipe for success
  • Innovative formal solutions that keep the monsters at bay
Speaker Bio: Sergio Marchese is the Technical Marketing Manager at OneSpin Solutions. He brings to this role 18 years of experience in the semiconductor and electronic design automation (EDA) industries.

Marchese started his career at Infineon Technologies, applying coverage-driven constrained-random simulation and formal methods to verify the TriCore CPU, an architecture widely used in automotive SoCs. He has since worked on projects in the communications, consumer, industrial and aerospace domains. Most recently, he served as verification expert at Huawei Technologies, leading formal verification activities for ARM CPU and consumer SoC designs. Marchese has built and managed state-of-the-art teams, successfully signing off complex hardware designs solely using formal verification.

Marchese holds a Master of Electronic Engineering degree from University of Catania, Italy. He has presented at several industry conferences in Europe and North America, and has published numerous technical papers.

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