ShellyH HS Edited

Shelly Henry

CEO | Founder,
Moores Lab AI

About the Speaker

Shelly Henry is CEO and Co-Founder of Moores Lab AI, where he is transforming semiconductor design and verification through agentic AI. With more than 20 years of experience in silicon engineering and AI, Shelly has led teams at Microsoft and ARM and contributed to more than 20 chip programs spanning Xbox, HoloLens, smartphones, cloud, and AI infrastructure. His deep expertise spans processor architecture, hardware engineering, and the end-to-end challenges of modern chip development. Shelly holds a Bachelor’s degree from IIT Madras and a Master’s degree from the University of Illinois Urbana-Champaign. He is focused on making advanced silicon innovation faster, more accessible, and dramatically more scalable.

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The Verification Gap: What AI Produces vs. What Silicon Demands

Overview

Every chip team has tried it: paste your spec into an LLM, watch a UVM testbench appear in seconds. The output looks plausible — monitors, drivers, a scoreboard, cover groups. Then a DV engineer looks at it. The testplan misses corner cases. The monitor doesn’t handle back-pressure. The scoreboard assumes in-order transactions. SVA properties are syntactically correct but semantically wrong. The coverage model samples signals instead of closing design intent. This talk walks each artifact — testplan, testbench components, testcases, SVA, and functional coverage — showing where AI falls short today, what production DV requires, and what it takes to close the gap.

Key Points

  • The surface looks right — the depth doesn’t. Production DV is about semantic correctness: does the monitor actually capture the protocol’s handshaking behavior? Does the scoreboard handle out-of-order responses? Does the coverage model reflect what could go wrong, not just what the
    spec says should happen? The gap between “looks like a testbench” and “closes verification” is where most AI tools stop.
  • SVA and functional coverage are the hardest — and the most important. This is where DV earns its keep, and where AI consistently underperforms. Assertion properties miss disable conditions and use weak operators where strong ones are needed. Coverage models bin individual signals without cross-coverage or state-machine transition coverage.
  • Closing the gap isn’t a prompting problem — it’s an infrastructure problem. The path from AI-generated to production-ready requires constraint encoding (protocol invariants and timing relationships baked in at generation time, not asserted post-hoc), automated validation loops that catch semantic errors before a human reviews, and a system of record that tracks coverage closure.