Shankar Channabasappa
AVP Custom Silicon,
Tessolve Semiconductor Inc
About the Speaker
Shankar Channabasappa is a seasoned semiconductor technology leader with over two decades of experience spanning the complete ASIC development lifecycle, from architecture and specification through RTL design, verification, physical implementation, and GDSII signoff. He holds an M.S. in Electrical Engineering from the Indian Institute of Science (IISc), Bangalore, and has successfully built and led high-performance engineering teams across the United States and India.
As the leader of Custom ASIC Development and Turnkey Solutions at Tessolve Semiconductor Inc., Shankar drives the delivery of complex semiconductor products from concept to production. Prior to Tessolve, he spent more than 14 years at Broadcom and also contributed to several AI/ML startups, delivering multiple successful ASICs into production.
His expertise includes high-performance networking and AI/ML SoCs, PCIe Gen5/Gen6, DDR memory subsystems, high-speed Ethernet, 200G SerDes, Interlaken, and ARM-based SoC architectures. He has led the development of silicon-proven products in advanced technologies, including TSMC N3P, enabling industry-leading performance, power efficiency, and area optimization for cloud, AI, and data center applications.
System Verilog RTL generation using NL Specification with AI tools
Overview
How to generate System Verilog RTL using NL Specifications? It is possible now with AI tools such as Claude, Cadence ChipStack AI Super Agent, Alpha Design AI ChipAgents, and Synopsys.ai Copilot. These tools are transforming front-end semiconductor design by converting specifications, microarchitecture documents, interface definitions, and register maps into draft SystemVerilog RTL, assertions, and verification collateral.ChipStack and ChipAgents use multi-agent workflows with design-intent awareness, while Claude and other LLMs provide prompt-driven RTL generation and design assistance. These tools can significantly accelerate RTL development, verification planning, and debug activities.However, generated RTL still requires expert review, simulation, linting, CDC/RDC analysis, formal verification, and signoff before production use.
Key Points
- System Verilog RTL Generation using manual coding
- System Verilog RTL Generation using AI tools
- Current possibilities for RTL generation
