Paul Graykowski

About the Speaker

Paul Graykowski is a Product Marketing Director in the System Verification Group at Cadence, focused on Verification IP (VIP). With over 25 years of experience designing and verifying System on Chip (SoC) solutions, he has worked across simulation, mixed-signal verification, UVM, and verification methodology. More recently, Paul has been involved in sharing Cadence’s work on verification optimization and agentic AI. He previously held marketing and application engineering roles at Arteris and Synopsys, and worked in design and verification at Cirrus Logic, Compaq, and Intel. He received his BSEE from Texas A&M University.

Agentic AI in Verification: Introducing the ChipStack Super Agent

Overview

Semiconductor design complexity is outpacing traditional engineering capacity, driving EDA tools past point solutions toward agentic, AI-driven optimization. Cadence answers this shift with a family of AI agent stacks integrated directly into its tools to work alongside engineers. ChipStack™ Super Agent is the stack purpose-built for design verification: specialized agents that assist with test planning and coverage closure, formal testbench generation and debug, and regression debugging with auto-fix. ChipStack embeds within the engineer’s existing verification flow, coordinating tools and methodologies to accelerate each stage while keeping the engineer in control.

Key Points

• EDA is shifting from point solutions to agentic AI — the industry-level trend driving the need for ChipStack.
• ChipStack is one of several Cadence stacks being purpose-built for design verification — it’s a focused product, not a general-purpose AI layer
• It embeds into the existing verification flow rather than replacing it — agents accelerate test development, formal, and debug while engineers stay in control.