Jagadish Rongali

About the Speaker

Jagadish Rongali is a Senior Principal Engineer with 18+ years of experience delivering silicon‑proven SoC solutions across automotive, wireless, mobile, healthcare, and secure‑payment domains. He specializes in SoC/IP verification, FPGA prototyping, system‑level emulation, formal verification, low‑power verification, and RNM modeling. Jagadish has led complex verification programs at NXP and Goodix, improving coverage, quality, and silicon success. His work spans secure‑boot engines, DMA IP, RF‑digital interfaces, SerDes/DDR, and mixed‑signal subsystems. An active contributor to patents, publications, and industry forums, he also mentors engineers and drives automation initiatives that accelerate hardware bring‑up and reduce re‑spins.

DMA: The Hidden Engine Behind the AI performance – Architecture, Bottlenecks and Verification

Overview

Every AI SoC benchmarks its compute engine — but it’s the Direct Memory Access (DMA) engine that decides whether those TOPS numbers ever materialize in silicon. This talk makes the case that the DMA is the most underestimated block in modern AI SoC design.
We open with architecture — tracing the evolution from monolithic AXI masters to distributed, N-dimensional engines capable of on-the-fly tensor layout transformation, and explaining why software control loops remain the single biggest bandwidth killer in heterogeneous multi-accelerator systems today.
We then expose the bottlenecks engineers actually hit in production: AXI outstanding transaction limits, non-contiguous access penalties, descriptor fetch latency, ACE-Lite coherence overhead, and DRAM row-buffer sensitivity — none of which appear until your compute pipeline is fast enough to reveal them.
We close with verification — the discipline most under-resourced relative to its risk. Attendees will leave with a concrete UVM agent structure for AXI4/ACE-Lite environments, actionable SVA properties for descriptor integrity and forward-progress guarantees, and an FPV strategy for deadlock and starvation that simulation will never reliably catch.
Targeted at SoC architects, microarchitects, and verification engineers working at the memory-compute boundary.

Key Points

• The DMA is your AI SoC’s real performance bottleneck — not the compute engine
• Modern DMA architecture must co-evolve with AI workloads
• DMA verification is the highest-risk, lowest-investment block in most verification plans