Jagadish Rongali
Senior Principal Engineer,
NXP Semiconductors Inc
About the Speaker
Jagadish Rongali is a Senior Principal Engineer with 18+ years of experience delivering silicon‑proven SoC solutions across automotive, wireless, mobile, healthcare, and secure‑payment domains. He specializes in SoC/IP verification, FPGA prototyping, system‑level emulation, formal verification, low‑power verification, and RNM modeling. Jagadish has led complex verification programs at NXP and Goodix, improving coverage, quality, and silicon success. His work spans secure‑boot engines, DMA IP, RF‑digital interfaces, SerDes/DDR, and mixed‑signal subsystems. An active contributor to patents, publications, and industry forums, he also mentors engineers and drives automation initiatives that accelerate hardware bring‑up and reduce re‑spins.
DMA: The Hidden Engine Behind the AI performance – Architecture, Bottlenecks and Verification
Overview
DMA is becoming a key bottleneck in modern AI SoCs as compute scales. This talk outlines a generic DMA architecture and a verification approach combining UVM/SVA simulation, formal property verification, and emulation. It highlights deadlock/starvation‑proof design, formal methods for liveness and functional safety (ISO 26262), and the role of emulation for full‑workload stress testing. It also describes running simulation, formal, and emulation in parallel to accelerate schedules, and briefly explores a cost‑conscious RAG‑based workflow to support debug and triage.
Key Points
- As AI SoC compute scales, the DMA subsystem is increasingly recognized industry-wide as a first-class architectural concern, alongside compute and memory – a trend that can benefit overall system bandwidth, latency, and power
- Coverage closure alone is not the finish line: deadlock and starvation are systemic failure classes that simulation alone can miss, which is why formal property verification (FPV) is included as a core part of the methodology discussed here – the same formal engines extend to functional-safety-relevant properties (e.g., fault-detection, error-containment) referenced against standards such as ISO 26262, without claiming compliance, qualification, or certification to any standard
- Real-world performance validation – sustained bandwidth, multi-accelerator contention, and stress conditions – is best suited to emulation rather than simulation; emulation is where the DMA subsystem can be exercised against workload-scale traffic well before tapeout
