Event at a Glance
Tuesday 25th October, 2022
12:00 – 13:00 BST
FREE to attend Online
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Analog Mixed Signal Verification
Analog mixed signal chips continue to grow in both demand and complexity, and a consistent efficient verification approach remains a key topic for concern. In this DVClub Peter Grove of Renesas will present a Mixed Signal Universal TestBench for RTL/DMS/AMS
Welcome and Introduction
Mike Bartley, Senior Vice President – VLSI Design, Tessolve
|12.05 BST||A Mixed-Signal Universal Testbench for RTL/DMS/AMS (UTB)
Peter Grove, Renesas
|12.50 BST||Closing Remarks|
The principal goal of each DVCLUB meeting is to have fun while helping build the European verification community through regular educational and networking events. Attendance at DVClub Europe meetings is free and is open to all non-service provider semiconductor professionals. Each meeting addresses a specific issue faced by the design and verification community and whatever your speciality provides an excellent opportunity for updating knowledge as well as share experiences, insights and issues with other members of the verification community.
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