Chiranjeevi Sirandas
Senior Verification Engineer,
Nvidia
About the Speaker
Chiranjeevi Sirandas is a Senior Verification Engineer at NVIDIA with experience in ASIC microarchitecture, design, verification, and validation. His work spans PCIe-based DMA, SmartNICs, high-speed networking, and crossbar interconnects. He has developed testbenches at the chip, subsystem, and unit levels using SystemVerilog and UVM, including constrained-random and self-checking environments. His background also includes testbench architecture, test planning, system prototyping, and validation.
Extending UVM RAL for Application-Specific Register Verification
Overview
As hardware designs evolve, register verification must handle new access rules and a wider range of requirements. This presentation shows how to extend UVM RAL while keeping existing tests and sequences unchanged. It uses registers protected by access control as an example. The adapter selects a valid requestor for normal accesses. Extensions let tests choose invalid requestors to check that access is denied. A shared register database provides policy information, while the predictor helps keep the register model accurate. The approach focuses on simple design, easy maintenance, and support for future requirements with limited changes to the existing verification environment.
Key Points
- Extend UVM RAL for access control protected registers.
- Continue to use default UVM RAL sequences for access protected registers.
- Support directed negative testing through UVM RAL extensions.
