About Bill Gascoyne

Currently works at Blue Pearl Solutions in documentation, training, and software QA
Previously worked as an AE and in technical training at LSI Logic, and in technical training at Magma Design Automation

About Dammy Olopade

Dammy is a Technical Lead at Google, where he leads Quality and Innovation in building AI platforms. Previously at Intel, he built, managed and led teams as a technical contributor. His Quality work focused on the prevention of metastability issues, innovated new tools/solutions with leading EDA companies for CDC, RDC etc. His multi-disciplinary expertise has been essential in tackling complex challenges. His Innovation work centered on taking key technologies from incubation to products, making sure the culture/environment supported the nurturing of creative ideas, and the corporation appropriately invested in the future, as it focused on executing on the flagship projects. He is an avid mentor who prioritizes relationships (faith, family, friends)

CDC-RDC Verification Standard 1.0 for Interoperable Abstract Model

Overview

CDC-RDC analysis has evolved as an inevitable stage in RTL quality signoff in the last two decades. Over this period, the designs have grown exponentially to SOC’s having 2 trillion+ transistors and chiplet’s having 7+ SOC’s. Today CDC-RDC verification has become a multifaceted effort across the chips designed for clients, servers, mobile, automotives, memory, AI/ML, FPGA etc. with focus on cleaning up of thousands of clocks and constraints, integrating the SVA’s for constraints in validation environment to check for correctness, looking for power domain and DFT logic induced crossings, finally signing off with netlist CDC-RDC to unearth any glitches and corrupted synchronizers during synthesis.
As the design sizes increased in every generation, the EDA tools could not handle running flatly and the only way of handling design complexity was through hierarchical CDC-RDC analysis consuming abstracts. Also, hierarchical analysis helps to enable the analysis in parallel with teams across the globe. Even with all this significant progress in capabilities of EDA tools the major bottleneck in CDC-RDC analysis of complex SOC’s and Chiplets is consuming abstracts generated by different vendor tools. Different vendor tool abstracts are seen because of multiple IP vendors; even in-house teams might deliver abstracts generated with different vendors tools.

The Accellera CDC Working-Group aims to define a standard CDC-RDC IP-XACT/TCL model to be portable and reusable regardless of the involved verification tool.
As moving from monolithic designs to IP/SOC with IPs sourced from a small or select providers to sourcing IPs globally (to create differentiated products), the quality must be maintained as driving faster time-to-market. In areas where the standards (SystemVerilog, OVM/UVM, LP/UPF…) are present, the integration is able to meet the above (quality, speed). However, in areas where standards (in this case, CDC-RDC) are not yet available, most options trade off either quality, or time-to-market, or both. Creating a standard for inter-operable collateral addresses this gap.
This tutorial aims to review CDC-RDC Basic Concepts and constraints, as well as the description of the reference verification flow, and addressing the goals, scope, structure & deliverables of the Accellera CDC Working Group which continuously maintains and enhances the specification of the standard abstract model. Technical details, part of the first official LRM (Language Reference Manual) released on March 2nd, 2026, will be also presented.

Key Points

• Clock Domain Crossing Verification
• Standard Modelling
• Tcl & IP-Xact format