|Conference:||DVCLUB Europe | Performance Testing and Analysis|
|Speaker:||David Kelf ,Breker Verification Systems|
|Speaker Title:||Automated SoC Performance and Power Profiling Pre- and Post-Fabrication|
Sub-system and SoC level verification must include an analysis of potential performance and power issues. Indeed, SoC bugs are often of the form of bottlenecks in the system that slow down control and data flow to an unacceptable level for concurrent operation execution. We present a method to generate concurrent SoC and sub-system tests specifically targeted at performance and power issues that also include coherency, security and other factors that is in use today on multiple projects. This solution includes the measurement of concurrent execution coverage (3D-Coverage) to track areas requiring testing and discusses metrics to ensure thorough testing. It may be used pre-fabrication on simulation or emulation/prototyping, and then ported with no further effort to post-fabrication validation, and the visual inspection of results is made easily available in a specialized GUI.
Dave Kelf, is the CEO of Breker Verification Systems, the leader in test content synthesis using the PSS standard. Dave most recently served as vice president of worldwide marketing solutions at formal verification provider OneSpin Solutions. Earlier, Kelf was president and CEO of Sigmatix, Inc. He worked in sales and marketing at Cadence Design Systems, and was responsible for the Verilog and VHDL verification product lines. As vice president of marketing at Co-Design Automation and then Synopsys, Kelf oversaw the successful introduction and growth of the SystemVerilog language, before running marketing for Novas Software, noted for the Verdi product line, which became Springsoft and is now part of Synopsys.
Dave holds a Bachelor of Science degree in Electronic Computer Systems from the University of Salford and a Master of Science degree in Microelectronics from Brunel University, both in the U.K., and an MBA from Boston University.
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