Abinaya

About the Speaker

Abinaya is a Design Verification Engineer at NXP Semiconductors in Austin, Texas, working on UVM-based IP verification, CDC verification, and functional safety for automotive SoCs. Her work on AI-assisted regression optimization in UVM-based verification was presented at CSTIC 2026 and indexed in IEEE Xplore, and her current research focuses on LLM-assisted UVM testbench generation for RISC-V processors. She founded SiliconDV, an education platform for design verification engineers with an audience of over 10,000 and more than 50 engineers mentored. She holds a master’s from Boston University and a bachelor’s in Electronics and Communication Engineering from CEG, Anna University.

From Prompt to Passing Regression: LLM-Assisted UVM Testbench Bring-Up on an Open-Source RISC-V Core

Overview

Most AI-in-verification talks stop at the demo. This one starts after it. Using an open-source RISC-V core, this session walks through bringing up a UVM testbench with LLM assistance end to end: generating agents, sequences and scoreboard scaffolding, then closing the gap between code that compiles and code that catches bugs. It covers where the model saved real days, where it quietly cost time through hallucinated APIs and plausible-but-wrong assertions, and the review discipline that separates the two. Attendees leave with a workflow they can try on their own testbench and an honest accounting of its limits.

Key Points

• A repeatable LLM-assisted flow for UVM bring-up — where prompting genuinely pays off (agents, sequences, register model, constraint drafting) and where hand-writing is still faster.
• The failure modes to plan for: hallucinated APIs, assertions that look correct but check nothing, and coverage that reads as complete but isn’t — plus the review checks that catch them.
• An honest accounting of the result: what actually changed in bring-up effort and debug time on a real RISC-V testbench, and what didn’t.