Sandeep Sharma
Analog & Mixed Signal Design Verification Engineer,
Meta (Reality Labs)
Analog & Mixed Signal Design Verification Engineer,
Meta (Reality Labs)
Product Engineering: Analog Mixed Signal (AMS),
Cadence Design Systems
Sandeep Sharma
Sandeep Sharma is an Analog & Mixed Signal Design Verification Engineer at Meta Reality Labs, focused on mixed-signal verification methodology for analog IP and SoCs, spanning UVM-based AMS co-simulation, SystemVerilog real-number modeling and AI-assisted automation. Sandeep presented a UVM-based AMS co-simulation methodology at DVCon US 2024 and is passionate about bringing the rigor of digital verification to analog.
Vijay Akkaraju
Vijay Akkaraju works in AMS Product Engineering at Cadence Design Systems, partnering with customers and R&D on verification flows. Vijay brings 25+ years of mixed-signal experience, including IC design at Analog Devices and 14 years as an AMS specialist at Synopsys.
Overview
Analog content in modern SoCs keeps growing, yet AMS verification still lags digital in automation. This talk outlines a practical path to close that gap. It first revisits a UVM-based, digital-on-top methodology presented at DVCon US 2024, in which one testbench drives both SystemVerilog real-number models and SPICE netlists, enabling nightly mixed-signal regressions, constrained-random stimulus and assertions on analog nets. It then explores how AI agents can remove the next bottleneck, behavioral modeling, by generating models, checkers and testbenches from schematics, and closes with five high-impact opportunities for agentic AI across analog design and verification.
Key Points