Amit Kumar
Principal Engineer,
Tenstorrent
Principal Engineer,
Tenstorrent
Amit Kumar is a Principal Engineer in RISC-V Design Verification at Tenstorrent, based in Austin, Texas. His work focuses on verifying high-performance RISC-V cores, with particular emphasis on memory-management units, functional coverage, and scalable verification infrastructure. He leads development of reusable verification frameworks that combine UVM, RiESCUE, and Whisper, and actively drives open-source collaboration and tool adoption, including Verilator. Amit also contributes to verification of non-coherent atomics, vector extensions, and functional-safety features. Passionate about rigorous, evidence-driven engineering, he enjoys turning complex verification challenges into practical methodologies that improve confidence, productivity, and adoption across the broader RISC-V engineering community and beyond.
Overview
Every RISC-V DV team builds the same four layers around its RTL: stimulus, reference model, testbench environment and checking. Tenstorrent has open-sourced all four as separable, production-grade components: RiescueD/RiescueC/CTK for directed and compliance test generation, Whisper as a steppable golden model, rv_tester as a lockstep core testbench with platform models, and CoreArchCoverage for ISA coverage derived from the model. This talk walks the stack end to end, shows it running on CVA6 and OpenC910, then scopes the same four roles down to a unit-level MMU environment. Attendees leave knowing which piece to adapt first.
Key Points