Shelly Henry
CEO | Founder,
Moores Lab AI
CEO | Founder,
Moores Lab AI
Shelly Henry is CEO and Co-Founder of Moores Lab AI, where he is transforming semiconductor design and verification through agentic AI. With more than 20 years of experience in silicon engineering and AI, Shelly has led teams at Microsoft and ARM and contributed to more than 20 chip programs spanning Xbox, HoloLens, smartphones, cloud, and AI infrastructure. His deep expertise spans processor architecture, hardware engineering, and the end-to-end challenges of modern chip development. Shelly holds a Bachelor’s degree from IIT Madras and a Master’s degree from the University of Illinois Urbana-Champaign. He is focused on making advanced silicon innovation faster, more accessible, and dramatically more scalable.
Overview
Every chip team has tried it: paste your spec into an LLM, watch a UVM testbench appear in seconds. The output looks plausible — monitors, drivers, a scoreboard, cover groups. Then a DV engineer looks at it. The testplan misses corner cases. The monitor doesn’t handle back-pressure. The scoreboard assumes in-order transactions. SVA properties are syntactically correct but semantically wrong. The coverage model samples signals instead of closing design intent. This talk walks each artifact — testplan, testbench components, testcases, SVA, and functional coverage — showing where AI falls short today, what production DV requires, and what it takes to close the gap.
Key Points