Krupa Shah

About the Speaker

Krupa Shah is an ASIC Engineering Technical Leader at Cisco Systems in San Jose and an IEEE Senior Member. With over 20 years in the semiconductor industry, she specializes in verification across IP, subsystem, SoC, and multi-die levels using System Verilog and UVM. She is also a co-author of a paper under-review at IEEE Micro on GenAI-era chiplet verification. Her work focuses on multi-chiplet SiP integration and verification closure, with deep experience in PCIe, AMBA, DDR MultiPHY, and SerDes. Previously contributed at Intel/Altera, Synopsys, and Cadence, she led NiosV RISC-V verification, Open FPGA Stack and PCIe acceleration programs.

When 100% Coverage Isn’t Enough: Verifying Multi-Chiplet GenAI Platforms

Overview

Your chiplet passed verification. Your partner’s chiplet passed verification. Yet integration failures still appear at die boundaries. The presentation outlines the major verification problems emerging in GenAI-era platforms and the methodology evolution needed across tools, flows, and industry standards. It goes deeper into challenges like limited visibility into encrypted vendor models, poor reuse of pre-silicon environments, coverage that stops at die edges, and debug that loses context across package boundaries. GenAI workloads amplify these gaps through greater scale, vendor heterogeneity, and faster integration pressure.

Key Points

• Multi-chiplet integration systemic gaps: visibility, reuse, coverage, and cross-die debug/security. Monolithic SoC flows were never designed to handle these challenges.
• GenAI platforms amplify chiplet count, vendor diversity, and integration complexity. Turning today’s verification pain points into tomorrow’s sign-off blockers.
• Recommendations: The industry must move from die-level verification to platform-level integration verification through better vendor deliverables, cross-die coverage models, standardized debug observability, and stronger integration sign-off criteria.