David Landoll

About the Speaker

David Landoll is a Product Manager within Siemens EDA focused on formal and static verification technologies, including formal verification, static analysis, CDC, and AI-assisted verification solutions. With more than 30 years of experience in semiconductor verification, David has helped develop and deploy advanced verification methodologies used by many of the industry’s leading semiconductor companies. His work spans formal verification, safety and security verification, design signoff, and the application of AI to improve verification productivity. David is a frequent speaker at industry conferences and technical events and serves on the DVCon Technical Program Committee.

The Future of Formal Verification: Scaling Proof, Productivity, and Adoption with AI

Overview

As design complexity continues to accelerate, verification teams are under increasing pressure to find bugs earlier, close coverage faster, and improve productivity. Formal verification is increasingly being deployed beyond traditional property checking to address connectivity, security, coverage closure, processor verification, and signoff challenges. At the same time, automation and AI-assisted workflows are lowering adoption barriers and enabling wider use across engineering teams. This presentation examines the evolution of formal verification, shares lessons from real-world deployments, explores the opportunities and limitations of AI-assisted verification, and discusses how formal methodologies may continue to evolve in the years ahead.

Key Points

• Formal Is Expanding Beyond Property Checking
• AI Is Lowering the Barrier to Formal Adoption
• The Future of Formal Is Scale