ML (Machine Learning) is transforming the way we work in a wide range of industries and this has been accelerated by generative AI (Artificial Intelligence) applications such as ChatGPT. In this presentation we investigate how ML and AI can potentially be applied in DV (Design Verification), from automation of requirements/specification analysis and test plan generation, through test bench creation and test generation, to debug and coverage closure.

There is a very wide range of ML techniques available and this presentation first surveys those techniques and how they have been applied (successfully and unsuccessfully) to DV in both academia and in real projects. The objective is to better understand how to apply the most promising techniques to a wide range of DV activities to ultimately make DV both more efficient and effective.

The main objective of the presentation is to give the audience a better understanding of what is achievable of applying ML in DV and to give practical suggestions on their adoption.

Key Points:

• Overview of the various ML techniques
• Better understanding of the potential applicability of ML to DV
• Practical advice and experience of applying ML to DV

Meet Jagadeesh Jonna, a seasoned professional with a 17 years of experience in the realm of High Serial Speed Protocols. Having navigated through the intricate worlds of PCIE, USB, and Ethernet, Jagadeesh Jonna boasts a profound understanding of these critical technologies. His expertise extends across a diverse range of domains, including Mobile, IoT, Network, and Storage, allowing them to gain valuable insights into multiple industries. Throughout his career, he has been involved in numerous IP and SOC projects, collaborating with a diverse array of esteemed clients. With a track record of excellence and an insatiable appetite for innovation and continues to be a driving force in the ever-evolving landscape of technology.