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PSV – Development and Validation

Job Posted On

27-02-2023 19:14:41

Company Group

Tessolve Semiconductor Private Limited

Department

Services

Employee Type

Regular Employee - Probation

Designation

Technical Lead

Location

Noida, Uttar Pradesh, India (TESIN-ND)

Experience Required

6 - 10 years

Job Summary

Position: PSV – Design & Application Dev / Lab Validation and Characterization

Experience Level: 6 -10 years

Location –Noida

Tessolve Semiconductors a venture of Hero Electronix, part of $5B Hero Group companies a Design and Test Engineering Service Company providing End to End Solutions from Product Engineering, Software, Hardware, Wireless, Automotive and Embedded Solutions. Currently we are 2300+ employees worldwide. We are Global Multi- National Company having Engineering and Sales presences in India, Malaysia, Singapore, USA, UK, Europe, and China. Tessolve has strategic and sustainable growth plan to ensure the business stability to our valued customers and to protect the career of our employees even under disturbed Business situations.

Skills Required:

To be successful in this role you will:

- An integral part of R&D, working on projects at the state of the art of image sensor technology targeting various markets and applications.

- As a Functional Validation Engineer, you will be involved in validating all the division's products.

-Strong knowledge of FPGA prototyping and on circuit silico

- Experience and knowledge of C /python programming and good knowledge on real time Embedded electronics and computing

-Should have good understanding and strong knowledge on version management tools i.e., Git, CVS, SVN etc

-Should have Excellent hardware knowledge and debug capabilities on both hardware and software levels.

- Laboratory experience, including hands-on use of equipment: Oscilloscope, Signal generator, Logic analyser, etc.

- Experience and good understanding on High/Low speed Transmission Protocol like I2C,I3C,SPI,MIPI

-Should have experience and good knowledge on Jenkin, Gerrit etc Automation tools

-Notation of Imaging processing would be an added advantage

- Collaborating with cross functional HW and SW teams to solve complex issues and improve efficiency

- Good written and oral communication skills

-Strong analytical/problem solving skills, ability to learn quickly, and pronounced attention to detail

-Self-motivated, a good team player

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ML Verification Turns Convention on its Head

The verification of processor architectures designed for Machine Learning (ML) applications represent a departure from conventional techniques. Conventional constrained random testbenches, which focus on stimulus driving coverage, cannot scale for many ML algorithm realizations. ML architectures involve neural networks of processors that “learn” by manipulating coefficients across the network to match ideal outputs to a large quantity of input data. Furthermore, smart compiler technology is employed to leverage the many paths available in the network. An effective verification strategy can leverage planning algorithms that start with the desired output and optimize input values to achieve that output. Ensuring the paths that the compiler might trigger have all been tested, and that the test content can scale from individual processors to the entire network are critical challenges. Breker will share various approaches to this problem, developed through cooperation with three noted AI processor providers.

3 Key Points:

Current verification methodologies cannot scale to meet ML processor challenges

ML verification approach: consider desired outputs, optimize inputs to match

Test Suite Synthesis enable planning algorithm approach to target ML requirements

An Emulation Strategy for Artificial Intelligence Designs

The emergence of Artificial Intelligence is the “next big thing” and presents a unique opportunity for disruptive semiconductor development. End applications could range from ADAS, to 3D facial recognition, to voice and image processing, or to intelligent search. The SoCs for AI applications whether targeted for training or inference will have their own unique characteristics, but present quite common verification challenges that we will present in this session.

Supporting designs as big as 15 billion gates, Mentor’s Veloce Strato has unique virtualization capabilities that enable highly accurate pre-silicon execution of AI benchmarking applications like MLPerf. The Veloce Power App enables analysis of peak and average. We will cover how Veloce Strato and its supporting solutions are the best tool to help address the verification challenges of SoCs targeted for AI applications.

3 Key Points:

Deterministic solution for AI chips verification

Full virtual solution for HW/SW verification

TERAOPS/Watt assessement prior silicon availability

Job Description

PSV – Development and Validation

Solutions

Sector & Support

Insights

ML Verification Turns Convention on its Head

AI chips must get the math right

An Emulation Strategy for Artificial Intelligence Designs

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