Job Description

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Labview and Teststand - Lead Engineer / Technical Lead

Job Posted On

10-03-2023 13:26:40

Company Group

Tessolve Semiconductor Private Limited

Department

Services

Employee Type

Regular Employee - Probation

Designation

Technical Lead

Location

Electronic City, Bengaluru, Karnataka, India (TESIN-EC)

Experience Required

7 - 10 years

Job Summary

Position - Labview and Teststand

Experience - 7-10 Years

Location - Bangalore

JD:-

Completed his/her Bachelors orMaster in ECE or EEE related fields

7 to 10 years of experiencein Labview and Teststand

Experience in Digital IPValidation/SoC Validation

Experience in using Labequipment’s [e.g. Power supplies, DMM, SMU, Oscilloscopes etc..] is required

Should have good ‘C’programming skills

Know-how of the low-leveldrivers usage

Experience of the Lauterbach,Trace32 is required

Know-how of using Automationtools NI (National Instruments) tools such as LabView, Test Stand, phyton, perlis preferrable

About Tessolve Semiconductors :

Tessolve Semiconductors a venture of Hero Electronix, part of $5B Hero Group companies a Design and Test Engineering Service Company providing End to End Solutions from Product Engineering, Software, Hardware, Wireless, Automotive and Embedded Solutions. Currently we are 2000+ employees worldwide. Company has aggressive growth plan across all verticals including more than 50% Growth in the VLSI Domain year on year both Analog and Digital Side. Tessolve is a preferred vendor for most of the Semiconductor IP/ Product companies across the world. We are Global Mutli- National Company having Engineering and Sales presences in India, Malaysia, Singapore, USA, UK, Europe and China. Tessolve has strategic and sustainable growth plan to ensure the business stability to our valued customers and to protect the career of our employees even under disturbed Business situations.

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ML Verification Turns Convention on its Head

The verification of processor architectures designed for Machine Learning (ML) applications represent a departure from conventional techniques. Conventional constrained random testbenches, which focus on stimulus driving coverage, cannot scale for many ML algorithm realizations. ML architectures involve neural networks of processors that “learn” by manipulating coefficients across the network to match ideal outputs to a large quantity of input data. Furthermore, smart compiler technology is employed to leverage the many paths available in the network. An effective verification strategy can leverage planning algorithms that start with the desired output and optimize input values to achieve that output. Ensuring the paths that the compiler might trigger have all been tested, and that the test content can scale from individual processors to the entire network are critical challenges. Breker will share various approaches to this problem, developed through cooperation with three noted AI processor providers.

3 Key Points:

Current verification methodologies cannot scale to meet ML processor challenges

ML verification approach: consider desired outputs, optimize inputs to match

Test Suite Synthesis enable planning algorithm approach to target ML requirements

An Emulation Strategy for Artificial Intelligence Designs

The emergence of Artificial Intelligence is the “next big thing” and presents a unique opportunity for disruptive semiconductor development. End applications could range from ADAS, to 3D facial recognition, to voice and image processing, or to intelligent search. The SoCs for AI applications whether targeted for training or inference will have their own unique characteristics, but present quite common verification challenges that we will present in this session.

Supporting designs as big as 15 billion gates, Mentor’s Veloce Strato has unique virtualization capabilities that enable highly accurate pre-silicon execution of AI benchmarking applications like MLPerf. The Veloce Power App enables analysis of peak and average. We will cover how Veloce Strato and its supporting solutions are the best tool to help address the verification challenges of SoCs targeted for AI applications.

3 Key Points:

Deterministic solution for AI chips verification

Full virtual solution for HW/SW verification

TERAOPS/Watt assessement prior silicon availability

Name: Mike Bartley

Designation: Senior Vice President – VLSI Design

Title: Introduction

Biography:

Mike Bartley has a PhD in Mathematics from Bristol University, an MSc in Software Engineering, an MBA from the Open University and over 25 years of experience in software testing and hardware verification. He has built and managed state-of-the-art test and verification teams in a number of companies who still use the methodologies he established. Since founding TVS in 2008 he has grown the company to over 100 employees worldwide. Dr Bartley is Chair of both the Bristol branch of the British Computer Society and the West of England Bristol Local Enterprise Partnership (LEP). He has had over 50 articles and presentations published on the subjects of hardware verification, software testing and outsourcing.

Job Description

Labview and Teststand - Lead Engineer / Technical Lead

Solutions

Sector & Support

Insights

ML Verification Turns Convention on its Head

AI chips must get the math right

An Emulation Strategy for Artificial Intelligence Designs

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