Software V&V

V&V of Cyber Physical Systems

Innovate UK: V&V of Cyber Physical Systems

In March 2016 we announced that T&VS had won a grant from Innovate UK, the UK’s innovation agency , to develop advanced Verification and Validation (V&V) techniques that can cope with the increasing size and complexity of modern Cyber Physical Systems (CPS). Read the press release.

Subsequently, in June 2016, it was confirmed that T&VS is the project lead and will be working with the University of Bristol and end user CPS developers, including Thales, Dyson and SCISYS, to better understand how to apply today’s proven hardware verification techniques to the verification of software, and specifically to investigate the tooling required for the successful testing of CPS control software.

What Can We Learn from Hardware Verification?

Developers of CPS have recognised that the current techniques for software V&V will not scale as CPS become increasingly complex. The hardware verification industry faced a similar issue 20 years ago and so developed new verification techniques to overcome them. These techniques are now widely adopted and developers are now able to verify that the increasingly complex hardware they create will meet its functional requirements quickly and efficiently so that it reaches its target market in a timely fashion.

“Cyber physical systems will start to touch every part of our life. From robotic vacuum cleaners and online orders delivered by drone, to autonomous cars. Ensuring such systems are fully tested and safe to use can be both expensive and time consuming and thus a potential barrier to market entry. This Innovate UK project will investigate if verification techniques successfully adopted in hardware can be adapted to work with complex CPS software.”

Project Blog and Additional Resources

Slides: Training on “Advanced Verification Techniques” used in the first meeting
Slides : “Functional Coverage” and assertions from the first meeting

Project Background

The T&VS project is part of the Innovate UK and Defence Science and Technology Laboratory (DSTL) competition for funding that is investing up to £580,000 into ‘Software Verification & Validation for Complex Systems’. The funding is aimed at stimulating innovation throughout the software development lifecycle (SDLC) while focusing on the verification and validation (V&V) of two classes of complex systems: Cyber Physical Systems (CPS) and systems with emergent behaviours.

Innovate UK is the UK’s innovation agency. It works with people, companies and partner organisations to find and drive the science and technology innovations that will grow the UK economy. For further information, visit: www.innovateuk.gov.uk

Contact

For additional information on the project please contact Dr. Mike Bartley (T&VS Founder and CEO) at: mike@testandverification.com

ML Verification Turns Convention on its Head

The verification of processor architectures designed for Machine Learning (ML) applications represent a departure from conventional techniques. Conventional constrained random testbenches, which focus on stimulus driving coverage, cannot scale for many ML algorithm realizations. ML architectures involve neural networks of processors that “learn” by manipulating coefficients across the network to match ideal outputs to a large quantity of input data. Furthermore, smart compiler technology is employed to leverage the many paths available in the network. An effective verification strategy can leverage planning algorithms that start with the desired output and optimize input values to achieve that output. Ensuring the paths that the compiler might trigger have all been tested, and that the test content can scale from individual processors to the entire network are critical challenges. Breker will share various approaches to this problem, developed through cooperation with three noted AI processor providers.

3 Key Points:

Current verification methodologies cannot scale to meet ML processor challenges

ML verification approach: consider desired outputs, optimize inputs to match

Test Suite Synthesis enable planning algorithm approach to target ML requirements

An Emulation Strategy for Artificial Intelligence Designs

The emergence of Artificial Intelligence is the “next big thing” and presents a unique opportunity for disruptive semiconductor development. End applications could range from ADAS, to 3D facial recognition, to voice and image processing, or to intelligent search. The SoCs for AI applications whether targeted for training or inference will have their own unique characteristics, but present quite common verification challenges that we will present in this session.

Supporting designs as big as 15 billion gates, Mentor’s Veloce Strato has unique virtualization capabilities that enable highly accurate pre-silicon execution of AI benchmarking applications like MLPerf. The Veloce Power App enables analysis of peak and average. We will cover how Veloce Strato and its supporting solutions are the best tool to help address the verification challenges of SoCs targeted for AI applications.

3 Key Points:

Deterministic solution for AI chips verification

Full virtual solution for HW/SW verification

TERAOPS/Watt assessement prior silicon availability

Name: Mike Bartley

Designation: Senior Vice President – VLSI Design

Title: Introduction

Biography:

Mike Bartley has a PhD in Mathematics from Bristol University, an MSc in Software Engineering, an MBA from the Open University and over 25 years of experience in software testing and hardware verification. He has built and managed state-of-the-art test and verification teams in a number of companies who still use the methodologies he established. Since founding TVS in 2008 he has grown the company to over 100 employees worldwide. Dr Bartley is Chair of both the Bristol branch of the British Computer Society and the West of England Bristol Local Enterprise Partnership (LEP). He has had over 50 articles and presentations published on the subjects of hardware verification, software testing and outsourcing.

Software V&V

V&V of Cyber Physical Systems

Innovate UK: V&V of Cyber Physical Systems

What Can We Learn from Hardware Verification?

Project Blog and Additional Resources

Project Background

Contact

Solutions

Sector & Support

Insights

ML Verification Turns Convention on its Head

AI chips must get the math right

An Emulation Strategy for Artificial Intelligence Designs

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