Private Trials – UX

When releasing a new product to customers it is essential to gain initial feedback on the experience from friendly users. Managing this trial and gaining valuable insight can be extremely difficult.

Tessolve has developed an innovative solution that utilises a crowd testing community to create a specific group of users matching your exact requirements, allowing an invaluable insight into your products performance from real users in the real world.

Benefits

Bespoke crowd of testers in the real world
Matching your exact customer requirements including (but not limited to): location / demographics / devices / platforms.
Real users that are testers, that are incentivised to find and raise valid defects
Gain confidence your customers will be delighted with the product

Example Engagement Scenario

IOT Health Fitness Tracker: The customer wanted to gain feedback on the products performance with real users across the globe, using the device in their day to day lives. A private trial UX was established and a crowd built to meet the requirements and delivered to ensure the client received maximum customer experience feedback.

Smart Metering: A smart metering company wanted to understand the exact performance of a new communications hub before rolling it out across a vast customer base. A private trial UX was established and a crowd built to meet the exact location and demographics specified, allowing the client to fully understand the performance of the product in a variety of housing.

Tessolve can also work with clients to help ensure the correct security features are built into devices at the outset and processes to assist with ongoing maintenance and updates.

Crowdsourced Testing with Tessolve

Tessolve global crowd of 55,000 expert testers across 145 countries, benefits include:

Management of the remote workforce, with summary reports on bugs found
Detailed defect reporting including: process description, results, frequency and screenshots
Combine a Tessolve Software Testing team for all your onsite testing requirements with Crowd Software Testing

Additional information on Tessolve Crowdsourced Testing services.

Find Out More

Contact one of our consultants today to discuss your requirements.
No hard sales, just pertinent questions to understand your needs and to discuss how we may be able to help.

Alternatively contact one of our Local Sales Offices.

Get in Touch

ML Verification Turns Convention on its Head

The verification of processor architectures designed for Machine Learning (ML) applications represent a departure from conventional techniques. Conventional constrained random testbenches, which focus on stimulus driving coverage, cannot scale for many ML algorithm realizations. ML architectures involve neural networks of processors that “learn” by manipulating coefficients across the network to match ideal outputs to a large quantity of input data. Furthermore, smart compiler technology is employed to leverage the many paths available in the network. An effective verification strategy can leverage planning algorithms that start with the desired output and optimize input values to achieve that output. Ensuring the paths that the compiler might trigger have all been tested, and that the test content can scale from individual processors to the entire network are critical challenges. Breker will share various approaches to this problem, developed through cooperation with three noted AI processor providers.

3 Key Points:

Current verification methodologies cannot scale to meet ML processor challenges

ML verification approach: consider desired outputs, optimize inputs to match

Test Suite Synthesis enable planning algorithm approach to target ML requirements

AI chips must get the math right

Most AI chips and hardware accelerators that power machine learning (ML) and deep learning (DL) applications include floating-point units (FPUs). Algorithms used in neural networks are often based on operations that use multiplication and addition of floating-point values. FPUs are difficult to implement. The IEEE 754 standard defines many corner-case scenarios and non-ordinary values. Even a minor rounding mistake could accumulate over many iterations and produce a large error. An FPU formal verification app compliant with IEEE-754 provides an efficient and rigorous solutions to FPU functional verification

3 Key Points:

Floating-point unit (FPU) for AI chips

FPU Formal Verification App

Compliance with IEEE-754

An Emulation Strategy for Artificial Intelligence Designs

The emergence of Artificial Intelligence is the “next big thing” and presents a unique opportunity for disruptive semiconductor development. End applications could range from ADAS, to 3D facial recognition, to voice and image processing, or to intelligent search. The SoCs for AI applications whether targeted for training or inference will have their own unique characteristics, but present quite common verification challenges that we will present in this session.

Supporting designs as big as 15 billion gates, Mentor’s Veloce Strato has unique virtualization capabilities that enable highly accurate pre-silicon execution of AI benchmarking applications like MLPerf. The Veloce Power App enables analysis of peak and average. We will cover how Veloce Strato and its supporting solutions are the best tool to help address the verification challenges of SoCs targeted for AI applications.

3 Key Points:

Deterministic solution for AI chips verification

Full virtual solution for HW/SW verification

TERAOPS/Watt assessement prior silicon availability

Name: Mike Bartley

Designation: Senior Vice President – VLSI Design

Title: Introduction

Biography:

Mike Bartley has a PhD in Mathematics from Bristol University, an MSc in Software Engineering, an MBA from the Open University and over 25 years of experience in software testing and hardware verification. He has built and managed state-of-the-art test and verification teams in a number of companies who still use the methodologies he established. Since founding TVS in 2008 he has grown the company to over 100 employees worldwide. Dr Bartley is Chair of both the Bristol branch of the British Computer Society and the West of England Bristol Local Enterprise Partnership (LEP). He has had over 50 articles and presentations published on the subjects of hardware verification, software testing and outsourcing.

Private Trials – UX

Benefits

Example Engagement Scenario

Crowdsourced Testing with Tessolve

Find Out More

Solutions

Sector & Support

Insights

ML Verification Turns Convention on its Head

AI chips must get the math right

An Emulation Strategy for Artificial Intelligence Designs

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