Tessolve
  • Company
    • About
    • Leadership
    • Board of Directors
    • Quality
    • Partners
  • Silicon Engineering
    • Chip Solutions
      • VLSI Design
        • Analog & Mixed Signal
        • RTL Design
        • SystemC Solutions
        • Design Verification (DV)
        • Design for Test (DFT)
        • Physical Design
        • FPGA Emulation & Validation
      • Test Engineering
      • Product Engineering
    • Hardware Solutions
  • Embedded Solutions
    • SOM & EVK Solutions
      • NXP
      • Qualcomm
      • Mediatek
      • Texas Instruments
    • Digitization Solutions
      • IoT Solutions
      • AI Solutions
      • Cloud Services
    • Wireless Testing
    • Software Solutions
      • Automation
      • Software Testing
      • System Integration
  • Industry
    • Automotive
      • TERA
    • Avionics
    • Consumer Electronics
    • Fintech
    • Industrial
    • Medical
      • Healthcare
    • Wireless Telecom
    • Sensors
  • Infrastructure
    • Test Floor
    • PCB Fab
    • Failure Analysis
    • STPI Smart Lab
  • Insights
    • News
    • Events
      • DVClub
      • Verification Futures
    • Brochures & White Papers
    • Case Studies
    • Customer Testimonials
    • Thought Leadership Blogs
    • Research Update
  • Careers
  • Contact
Turnkey Test Solution on T2000 platform for Wafer Sort and Final Test Hardware
Our Customer, a leading semiconductor company in the automotive space, provides high-performance mix..
Download PDF
Turnkey Test Solution for Flow Sensor Testing and Calibration
Our Client designs, manufacture, and markets low-power, high-performance mixed-signal semiconductor ..
Download PDF
Low Power Verification of CPU Subsystem for a Mobile Platform Device
Our Client’s mobile platform is a suite of system on a chip (SoC) semiconductor products designed an..
Download PDF
Turnkey Solution for Grade 2, AEC-Q100 Automotive Wireless Standard
Our Client’s Car-to-car communication system is attracting significant attention as it promises to d..
Download PDF
Test Solution for a 3D Image Processor Device
Test Engineering Solution Developed through Immense Challenges for a 3D Image Processor Chip used fo..
Download PDF
Test Solution for Car-to-Car Communication Systems
The Client’s Communication chip is a low power processor which can be used in intelligent traffic sy..
Download PDF
Turnkey Test Solution for A First gen ASIC, an IoT Product for Voice Service
Our Client’s Speech Understanding Engine Processor is a First gen ASIC for discrete audio DSP and au..
Download PDF
Test Solution for an ASIC, for an IoT Application
Our Client’s Mixed signal chip is part of Wafer Level Chip Scale Package (WLCSP) for IoT Application..
Download PDF
Testing Precision Voltage Regulators
This was a conversion project were a series of precision voltage regulators ( fixed & Variable type)..
Download PDF

Download Brochure

    Solutions

    • Chip Solutions
    • Hardware Solutions
    • Embedded Solutions
    • IoT Solutions

    Sector & Support

    • Industry
    • Infrastructure

    Insights

    • About
    • Leadership
    • Careers-old
    • News
    • Case Studies
    • Contact

    © 2019 Tessolve. | Agency Partner - Talkd.

    Privacy Policy

    • Company
      • About
      • Leadership
      • Board of Directors
      • Quality
      • Partners
    • Silicon Engineering
      • Chip Solutions
        • VLSI Design
          • Analog & Mixed Signal
          • RTL Design
          • SystemC Solutions
          • Design Verification (DV)
          • Design for Test (DFT)
          • Physical Design
          • FPGA Emulation & Validation
        • Test Engineering
        • Product Engineering
      • Hardware Solutions
    • Embedded Solutions
      • SOM & EVK Solutions
        • NXP
        • Qualcomm
        • Mediatek
        • Texas Instruments
      • Digitization Solutions
        • IoT Solutions
        • AI Solutions
        • Cloud Services
      • Wireless Testing
      • Software Solutions
        • Automation
        • Software Testing
        • System Integration
    • Industry
      • Automotive
        • TERA
      • Avionics
      • Consumer Electronics
      • Fintech
      • Industrial
      • Medical
        • Healthcare
      • Wireless Telecom
      • Sensors
    • Infrastructure
      • Test Floor
      • PCB Fab
      • Failure Analysis
      • STPI Smart Lab
    • Insights
      • News
      • Events
        • DVClub
        • Verification Futures
      • Brochures & White Papers
      • Case Studies
      • Customer Testimonials
      • Thought Leadership Blogs
      • Research Update
    • Careers
    • Contact

       

        Schedule a meeting to learn more about our Hardware Capabilities

          Name *

          E-mail *

          Organization *

          I'm Interested In *



              Name *

              E-mail *

              Company *

              Designation *


              ML Verification Turns Convention on its Head

              The verification of processor architectures designed for Machine Learning (ML) applications represent a departure from conventional techniques. Conventional constrained random testbenches, which focus on stimulus driving coverage, cannot scale for many ML algorithm realizations. ML architectures involve neural networks of processors that “learn” by manipulating coefficients across the network to match ideal outputs to a large quantity of input data. Furthermore, smart compiler technology is employed to leverage the many paths available in the network. An effective verification strategy can leverage planning algorithms that start with the desired output and optimize input values to achieve that output. Ensuring the paths that the compiler might trigger have all been tested, and that the test content can scale from individual processors to the entire network are critical challenges. Breker will share various approaches to this problem, developed through cooperation with three noted AI processor providers.

              3 Key Points:

            • Current verification methodologies cannot scale to meet ML processor challenges
            • ML verification approach: consider desired outputs, optimize inputs to match
            • Test Suite Synthesis enable planning algorithm approach to target ML requirements
            • AI chips must get the math right

              Most AI chips and hardware accelerators that power machine learning (ML) and deep learning (DL) applications include floating-point units (FPUs). Algorithms used in neural networks are often based on operations that use multiplication and addition of floating-point values. FPUs are difficult to implement. The IEEE 754 standard defines many corner-case scenarios and non-ordinary values. Even a minor rounding mistake could accumulate over many iterations and produce a large error. An FPU formal verification app compliant with IEEE-754 provides an efficient and rigorous solutions to FPU functional verification

              3 Key Points:

            • Floating-point unit (FPU) for AI chips
            • FPU Formal Verification App
            • Compliance with IEEE-754
            • An Emulation Strategy for Artificial Intelligence Designs

              The emergence of Artificial Intelligence is the “next big thing” and presents a unique opportunity for disruptive semiconductor development. End applications could range from ADAS, to 3D facial recognition, to voice and image processing, or to intelligent search. The SoCs for AI applications whether targeted for training or inference will have their own unique characteristics, but present quite common verification challenges that we will present in this session.

              Supporting designs as big as 15 billion gates, Mentor’s Veloce Strato has unique virtualization capabilities that enable highly accurate pre-silicon execution of AI benchmarking applications like MLPerf. The Veloce Power App enables analysis of peak and average. We will cover how Veloce Strato and its supporting solutions are the best tool to help address the verification challenges of SoCs targeted for AI applications.

              3 Key Points:

            • Deterministic solution for AI chips verification
            • Full virtual solution for HW/SW verification
            • TERAOPS/Watt assessement prior silicon availability
            • Name: Mike Bartley

              Designation: Senior Vice President – VLSI Design

              Title: Introduction

              Biography:

              Mike Bartley has a PhD in Mathematics from Bristol University, an MSc in Software Engineering, an MBA from the Open University and over 25 years of experience in software testing and hardware verification. He has built and managed state-of-the-art test and verification teams in a number of companies who still use the methodologies he established. Since founding TVS in 2008 he has grown the company to over 100 employees worldwide. Dr Bartley is Chair of both the Bristol branch of the British Computer Society and the West of England Bristol Local Enterprise Partnership (LEP). He has had over 50 articles and presentations published on the subjects of hardware verification, software testing and outsourcing.

              Please fill the form below

                Please fill the form below

                  Please fill the form below

                    Please fill the form below

                      Please fill the form below

                        Please fill the form below

                        [contact-form-7 404 "Not Found"]

                        Please fill the form below

                          SUBMIT YOUR RESUME

                            Attach Resume*

                            SUBMIT RESUME
                            [contact-form-7 404 "Not Found"]
                            [contact-form-7 404 "Not Found"]

                              Name *

                              E-mail *

                              Company *

                              Designation *


                                Name *

                                E-mail *

                                Company *

                                Designation *


                                  Name *

                                  E-mail *

                                  Company *

                                  Designation *


                                    Name *

                                    E-mail *

                                    Company *

                                    Designation *


                                      Name *

                                      E-mail *

                                      Company *

                                      Designation *


                                        Name *

                                        E-mail *

                                        Company *

                                        Designation *


                                          Name *

                                          E-mail *

                                          Company *

                                          Designation *


                                            Name *

                                            E-mail *

                                            Company *

                                            Designation *


                                            [contact-form-7 404 "Not Found"]
                                            [contact-form-7 404 "Not Found"]

                                              Name *

                                              E-mail *

                                              Company *

                                              Designation *


                                                Name *

                                                E-mail *

                                                Company *

                                                Designation *


                                                [contact-form-7 404 "Not Found"]

                                                  Name *

                                                  E-mail *

                                                  Company *

                                                  Designation *


                                                  [contact-form-7 404 "Not Found"]
                                                  [contact-form-7 404 "Not Found"]

                                                    Name *

                                                    E-mail *

                                                    Company *

                                                    Designation *


                                                      Name *

                                                      E-mail *

                                                      Company *

                                                      Designation *