asureVIP

A Broad Portfolio of Flexible and
Configurable Verification IP

asureVIP™ is a highly flexible and configurable verification portfolio which can be easily integrated into any complex digital SoC verification environment. Written natively in System Verilog or the e language for optimum performance, all of our VIP components are OVM/UVM or eRM compliant and can be provided as source code under our Flexible Licensing Model.

Flexible VIP Business Models

Licensing Model
Bespoke VIP Development
VIP Co-Development
VIP Enabled Services

The standard asureVIP portfolio covers five major verticals and Tessolve is also able to undertake bespoke VIP development:

ARM-based

All our ARM-based VIPs are highly optimized and proven to help customers exhaustively verify bus interconnects.

AMBA AXI (Advanced eXtensible Interface)
AMBA AXI Lite
AMBA ACE (AXI Coherency Extensions)
AMBA APB (Advanced Peripheral Bus)
AMBA AHB Lite (Advanced High-performance Bus)
AMBA CHI (Coherent Hub Interface)

Hi-Speed

The Tessolve High-Speed VIP is well positioned to address the burgeoning verification needs of the mobile SoC market.

CSIX (Common Switch Interface)
Ethernet (10/100 Mbps and 1/10Gbps)
PCIe EP (End Point)
PCIe RC (Root Complex)
SPI
USB

MIPI

The asure VIP portfolio for MIPI is well positioned to address the burgeoning verification needs of the mobile SoC market.

MIPI C-PHY
MIPI D-PHY
MIPI DSI (Display Serial Interface)
MIPI M-PHY
MIPI RFFE (RF Front End)
MIPI SMBUS
MIPI UniPro

Memory and Storage

With devices increasingly containing higher amounts of embedded/storage memory their verification has become a crucial step in SoC design.

DDR 4/3
LPDDR 4
NVMe
ONFI 3.2
SDCARD 4.0

Universal Serial IO

Tessolve specializes in providing highly flexible, independent and configurable VIP solutions for Serial IO protocols. Our customers have used our VIPs extensively to verify communications with low-speed devices.

CAN Bus (Controller Area Network)
GPIO
I2C
I2S
SMBUS

SPDIF
SPI
TDM
UART

Independent Verification Services

Tessolve can deliver an independent verification service that not only reduces development costs and time-to-to-market, but also improves product quality.

Receive the VIP Newsletter

The Tessolve ‘VIP Newsletter‘ is our regular newsletter covering Verification IP. To receive this or any of our other technology or conference related newsletters, please visit Tessolve Newsletters.

FREE VIP Evaluations

To help our customers evaluate the quality of the Tessolve VIP solutions, we are pleased to make some unit-level code samples and documentation available.

Find Out More

Contact one of our consultants today to discuss your requirements.
No hard sales, just pertinent questions to understand your needs and to discuss how we may be able to help.

Alternatively contact one of our Local Sales Offices.

Get in Touch

ML Verification Turns Convention on its Head

The verification of processor architectures designed for Machine Learning (ML) applications represent a departure from conventional techniques. Conventional constrained random testbenches, which focus on stimulus driving coverage, cannot scale for many ML algorithm realizations. ML architectures involve neural networks of processors that “learn” by manipulating coefficients across the network to match ideal outputs to a large quantity of input data. Furthermore, smart compiler technology is employed to leverage the many paths available in the network. An effective verification strategy can leverage planning algorithms that start with the desired output and optimize input values to achieve that output. Ensuring the paths that the compiler might trigger have all been tested, and that the test content can scale from individual processors to the entire network are critical challenges. Breker will share various approaches to this problem, developed through cooperation with three noted AI processor providers.

3 Key Points:

Current verification methodologies cannot scale to meet ML processor challenges

ML verification approach: consider desired outputs, optimize inputs to match

Test Suite Synthesis enable planning algorithm approach to target ML requirements

An Emulation Strategy for Artificial Intelligence Designs

The emergence of Artificial Intelligence is the “next big thing” and presents a unique opportunity for disruptive semiconductor development. End applications could range from ADAS, to 3D facial recognition, to voice and image processing, or to intelligent search. The SoCs for AI applications whether targeted for training or inference will have their own unique characteristics, but present quite common verification challenges that we will present in this session.

Supporting designs as big as 15 billion gates, Mentor’s Veloce Strato has unique virtualization capabilities that enable highly accurate pre-silicon execution of AI benchmarking applications like MLPerf. The Veloce Power App enables analysis of peak and average. We will cover how Veloce Strato and its supporting solutions are the best tool to help address the verification challenges of SoCs targeted for AI applications.

3 Key Points:

Deterministic solution for AI chips verification

Full virtual solution for HW/SW verification

TERAOPS/Watt assessement prior silicon availability

Name: Mike Bartley

Designation: Senior Vice President – VLSI Design

Title: Introduction

Biography:

Mike Bartley has a PhD in Mathematics from Bristol University, an MSc in Software Engineering, an MBA from the Open University and over 25 years of experience in software testing and hardware verification. He has built and managed state-of-the-art test and verification teams in a number of companies who still use the methodologies he established. Since founding TVS in 2008 he has grown the company to over 100 employees worldwide. Dr Bartley is Chair of both the Bristol branch of the British Computer Society and the West of England Bristol Local Enterprise Partnership (LEP). He has had over 50 articles and presentations published on the subjects of hardware verification, software testing and outsourcing.

asureVIP

A Broad Portfolio of Flexible and
Configurable Verification IP

Flexible VIP Business Models

ARM-based

Hi-Speed

MIPI

Memory and Storage

Universal Serial IO

Independent Verification Services

Receive the VIP Newsletter

FREE VIP Evaluations

Find Out More

Solutions

Sector & Support

Insights

ML Verification Turns Convention on its Head

AI chips must get the math right

An Emulation Strategy for Artificial Intelligence Designs

Please fill the form below

Please fill the form below

Please fill the form below

Please fill the form below

Please fill the form below

Please fill the form below

Please fill the form below

asureVIP

A Broad Portfolio of Flexible and Configurable Verification IP

Flexible VIP Business Models

ARM-based

Hi-Speed

MIPI

Memory and Storage

Universal Serial IO

Independent Verification Services

Receive the VIP Newsletter

FREE VIP Evaluations

Find Out More

Solutions

Sector & Support

Insights

A Broad Portfolio of Flexible and
Configurable Verification IP