The asureISG tool from Tessolve accelerates the completion of CPU code-coverage and helps discover bugs that often go unnoticed with traditional directed testing
The tool includes support for:
- Event generation for mimicking complex system (e.g. sensor inputs)
- Random generation of structures (e.g., directed graphs)
- Developed in pure C++
- Directly generate:
- Directed instruction assembly
- Constrained Random instruction assembly
- Special scenarios to verify CPU performance and corner cases
- Generate cases with sequences, constraints and policies
- Generate performance monitoring instruction streams, including:
- Various kinds of inputs, resources, resource sharing, etc.
- Configure specialized streams for specific unit-level instruction verification
Tessolve Extends CPU Verification Tool
The latest release of the Tessolve CPU verification tool, asureISG, packs a host of new Instruction Stream Generator features:
Verifying RISC-V SOCs
In the paper “A Hierarchical and Configurable Strategy to Verify RISC-V based SOCs” (presented at DVCon USA 2018) Tessolve outline a verification strategy for RISC-V based IP and SOCs using asureISG.
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