Tessolve offers Design for testability services to facilitate incorporation of appropriate test features into your design. The DFT team at Tessolve works closely with its test engineering team to ensure that most optimal testability solutions are offered keeping in view the targeted test platform.

The services offered on the DFT front are as follows:

 Define scan/memory test architecture for best test coverage

 Design DFT architecture and provide

 DFT specs including defining test buses for analog , test structures for testing analog macros like LVDS/DDR

  Proven skill set of defining DFT hooks and inserting DFT for mixed signal parts

  Scan, BIST, Boundary Scan using standard EDA tools

  ATPG vector generation

  At speed scan vectors ( transition model) vectors to catch the timing Failures using EDA tools like DSM-tmax tool.

  Ability to Validate DFT solutions provided using in-house Automated test equipment

  Generate Compressed and uncompressed test vectors to fit specific ATE capabilities

 Senior management has experience in taking more then 10 products from RTL to Production including 0.16/0.13micron/0.11 micron, 6 million gate , SOC to production in record time through innovative DFT hooks