Tessolve offers Design for testability services to facilitate incorporation of appropriate test features into your design. The DFT team at Tessolve works closely with its test engineering team to ensure that most optimal testability solutions are offered keeping in view the targeted test platform. The services offered on the DFT front are as follows:

DFT specification

• Define scan/memory test architecture for best test coverage
• Design DFT architecture and provide support to RTL designers to include DFT hooks in design from the beginning
• DFT specs including defining test busses for analog, test structures for testing analog macros like LVDS/DDR
• Define comprehensive test strategy early in design stage as per customer Test requirements for test and production chips
• Dedicated engineers specialized in Boundary SCAN and MBIST

DFT Insertion and Validation

• Proven skill set of defining DFT hooks and inserting DFT for mixed signal parts
• Scan, BIST, Boundary Scan using industry standard EDA tools for multi million gate designs implemented in sub-micron technologies
• Generate Compressed and Uncompressed test vectors to fit specific ATE capabilities
• Work closely with Physical Design and STA teams for timing closure and reduce number of iterations
• At speed scan vectors ( transition model ) to catch the timing Failures using EDA tools like DSM-tmax tool
• Ability to Validate DFT solutions provided using in-house Automated Test Equipment
• Ability to validate test vectors on post-route netlist with timing to ensure quality silicon

Post Silicon support

Capable of analyzing failures on ATE

DFT Experience / Capability

Tessolve engineering team has a rich experience in taking more then 10 products from RTL to Production including multi million gate SOCs in sub micron technologies in record time through innovative DFT hooks. The engineering team is capable of taking RTL or Netlist through all stages of DFT using Mentor or Synopsys tools.