|
Tessolve - PCB Division is having wide experience in designing custom Wirebond
and Flipchip BGA package designs. Our engineers work with many Fabs, Assembly
and Test houses to produce best IC packages. We also have in-house expertise to
do electrical and thermal modeling as well as SI and PI analysis.
Technology Selection
-
Expertise in designing Flip-Chip, WireBond BGA and CSP
-
WireBond
-
Cost effective and Flexible Process
-
2 - 6 Layer Substrate designs
-
4 layer and above results in best performance
-
Flip-Chip
-
Highest I/O count possible
-
Assembly cost independent of # of I/Os
-
Usage of Blind and Buried vias
-
Passive Integration in package
-
Leaded packages, Array packages
-
Design of MCMs
-
Design of MLO sand MLCs
-
Design of high pin count package
-
Selection of Substrate Material
Design Challenges
-
Growing complexity due to high speed signals
-
Reflection and Ringing
-
Optimal Power/GND Ball Placement & Plane Segmentation
-
Inter-pair Crosstalk
-
Propagation Delay Variations (skew)
-
IR Drop, SSN and proper selection of De-coupling Caps
-
Package selection & Validation and Driver Models
Required Inputs
-
Netlist
-
Die Size & Pad Coordinates
-
Package Type and Mechanical Drawing
-
Fab House Specification
-
Pin Use and Bus details
-
Std I/O Library and Buffer SPICE
| Planning &
Design |
 |
Optimize Stack up and Routing for
SI |
|
Best return
paths for all IOs |
|
Good Power and Ground coupling
|
|
Proper isolation among sensitive signal
groups |
|
Bump assignment
Optimization |
|
Optimal Power
and GND ball assignment |
|
Differential and Single Ended I/O
Planning |
|
Power and Ground does not get
chopped up |
|
SI driven Package pin out (GND-PWR
vs. signals) |
Signal & Power Integrity
-
Reflection and Ringing Analysis
-
Propagation delay variations (skew)
-
Single/differential Crosstalk Analysis
-
EMI Analysis
-
Single-ended I/O supply noise (SSN)
-
Core Supply Noise & Analysis
-
De-coupling Capacitors Estimation
-
MGH Analysis
-
S- parameter Analysis
Modeling (Electrical & Thermal)
-
Parasitic RLC Extraction
-
IBIS and S-parameter Model
-
Thermal Analysis-Theta Ja, Jb and Jc
-
Thermal Model and Nodal Temperature
Manufacturing Issues & CAM
-
Good in-house CAM team
-
Strict adherence to assembly and foundry specifications
-
Material selection for Pre-preg and Solder Mask
-
Coordination with assembly house and substrate foundry to achieve first time
right substrate
Package Type
|